Design of RF/IF analog to digital converters for software radio communication receivers

Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ± 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V supply

20 MHz IF bandpass switched capacitor [] modulator using a high performance OTA with NCFF compensation scheme

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references (leaves 91-93).Issued also on microfiche from Lange Micrographics.Switched capacitor (SC) circuits are widely used in many applications because of their accuracy and ease of integration in CMOS technology. They are not suitable for operation in high frequencies because of the settling time limitation of amplifiers. High frequency switched capacitor circuits pose challenging design specifications on the amplifiers which cannot be met by conventional circuit design techniques. High amplifier gain is required for an accurate output, whereas fast settling time is obtained by a high gainbandwidth (GBW) product. Amplifiers that use cascading of gain stages for obtaining high gain require some robust frequency compensation schemes, and usually have a low GBW, resulting in a slow settling time. This work proposes a new compensation scheme for high gain wideband amplifiers - No Capacitor Feed Forward (NCFF) compensation scheme. NCFF scheme uses pole-zero cancellation to obtain high gain, high GBW and a good phase margin. Left half plane (LHP) zeros produced due to the feedforward path causes a positive phase shift and is used to cancel the negative phase shift of poles. Fully differential and single ended operational transconductance amplifiers (OTA) using the proposed NCFF compensation scheme have been designed and fabricated using CMOS AMI 0.5 []m technology. The fully differential OTA has a gain of 97 dB, GBW of 350 MHz and a phase margin of around 90°. Sigma delta [ ] modulators use oversampling and quantization noise shaping to obtain a high dynamic range. They are well suited for use in radio and cellular systems to directly convert the narrowband IF signal centered at high frequencies to digital domain. Switched capacitor implementation of a [ ] modulator requires a fast settling amplifier to operate at high IF frequencies. The design and implementation issues of a 20 MHz IF, 80 MHz clock, fourth order switched capacitor bandpass [ ] modulator are discussed in detail. The modulator uses a high performance OTA using the proposed NCFF compensation scheme and it has been designed and fabricated using 3.3V CMOS TSMC 0.35 []m technology. The bandpass [ ] modulator has a peak SNR of 70 dB (post-layout simulations)